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Formal Verification Engineer

RAMAT HAHAYAL | R&D | FULL-TIME

NeuroBlade is looking for a Formal Verification Engineer to join our fast-growing engineering team. We are looking for brilliant and passionate people to join us and play a major role in building the next big thing in AI! If you enjoy working on cutting edge technologies and solving complex problems, and  have  team spirit and a can-do-attitude – Your place is with us!

NeuroBlade set out on a mission to redefine computer architecture for memory intensive tasks. We build high performance solutions for the rapidly growing AI & Analytics market while lowering total cost of ownership. NeuroBlade’s unique hardware solution paired with a complete end-to-end SW stack, enables businesses to take the next leap forward by increasing the efficiency and affordability of their data-centers.

WHAT YOU’LL BE DOING

  • Design, review and deploy formal verification environments using  Jasper or similar tools
  • Verify the design and hunt for bugs
  • Use state of the art  formal verification tools and technologies

REQUIRED

  • Deep understanding and proven experience in formal verification using Jasper or similar tools
  • Experience in writing SVA assertions
  • Scripting knowledge – perl, python, TCL, etc.
  • Electronics Engineering degree from a leading institution, graduated with honors

ADVANTAGES

  • Knowledge of AI/ML
  • Knowledge and experience in VLSI verification flow, languages & concepts
  • Experience in verification environments using SystemVerilog UVM
  • Experience in logic design, circuit design, and full chip integration

Click here to apply now.

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